Abstract Proceedings of ICIRESM – 2019
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DESIGN OF LOW POWER MULTI-MODULUS PRESCALAR USING PASS TRANSISTOR LOGIC
The high speed dual modulus prescaler is one of the important functional blocks in frequency synthesizers. The dual modulus prescaler design is bottleneck of the synthesizer it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) normally consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. In usually, dual modulus prescaler consist of flip flops and some extra logic implemented using logic gates which determine the terminal count. In here an E-TSPC logic based divide-by-2/3 prescaler using pass transistor logic is suitable for low supply voltage (0.9V) and low power applications is been designed and implemented. In here the counting logic and the mode selection control are implemented using a single p-mos transistor. Thus the critical path is reduced and also increases its working frequency. The Simulation results show that, compared with the conventional TSPC and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also the proposed 2/3 prescaler are designed and implemented to design a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler. The power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs its show that Simulation results. The CMOS TSMC 0.18μm technology is used to design a all prescalers and simulation using Mentor Graphics ELDO.
pass transistor, dual modulus
30/08/2019
6
19006
IMPORTANT DAYS
Paper Submission Last Date
October 20th, 2024
Notification of Acceptance
November 7th, 2024
Camera Ready Paper Submission & Author's Registration
November 1st, 2024
Date of Conference
November 15th, 2024
Publication
January 30th, 2025